The production of semiconductor components often entails the requirement that in one process step patterning by etching must be carried out, in which the sections to be removed are formed at least in part by silicon oxide or silicon nitride. One example of this is the fabrication of semiconductor memory cells which have a trench capacitor and a select transistor. Whereas the trench capacitor on one side is electrically connected to the select transistor by a buried strap, on the other side of the trench capacitor an insulation region (STI, shallow trench isolation) is produced, by means of which the trench capacitor is electrically insulated from an adjacent memory cell. The STI insulation region is produced by means of a patterning step in which a surface section formed by a partial section of the trench capacitor previously produced is removed. This means that not only silicon but also silicon oxide has to be etched, since the trench capacitor in its upper section has an insulation collar of silicon oxide. Since there is generally a silicon nitride layer at the surface of the section to be removed, it is therefore necessary for it to be possible for the etching process to etch silicon nitride as well.
With regard to the production of STI insulation regions during the fabrication of the memory cells, reference is made, by way of example, to the German laid-open specifications DE 199 41 148 A1 and DE 199 44 012 A1.
In view of the lateral dimensions of the trench capacitor, which are of the order of magnitude of 100-200 nm, the said process for producing the STI insulation region imposes extremely high demands on the positional accuracy, dimensional stability and flank steepness of the etching process to be employed, since the flank which is to be produced for the recess to be etched has to be located within the trench capacitor on the side remote from the buried strap with an extremely low lateral positioning inaccuracy.
To produce ultra small structures on the semiconductor surface and also to maintain extremely low variations in the feature sizes over the chip, the wafer or the batch, it is necessary for the reflection of light of the exposure wavelength at the wafer surface (photoresist—substrate interface) to be suppressed as completely as possible in order to eliminate disruptive interference effects. This applies in particular to exposure wavelengths at and below 248 nm (193 nm, 157 nm) on account of the increasing reflectivity of the substrates. Furthermore, to obtain the maximum possible depth of focus during the exposure, the resist layer which is to be exposed must firstly be as thin as possible. However, in order for the pattern to be transferred, in particular in the case of contact holes, a sufficient mask thickness and/or a high etching resistance of the mask (mask selectivity) matched to the layer thickness to be etched is required.
This problem can be countered by means of the following processes which are known from the prior art and are all based on the use of an additional auxiliary layer.
EP 0 492 253 A1 describes a photopatterning process in which two photoresist layers are used. An upper, relatively thin photoresist layer (top resist), after patterning with a silicon-containing agent, is made resistant to dry etching in the oxygen plasma. In this subsequent dry-etching step, the pattern of the top resist is transferred, with the precise dimension of the mask used for the patterning and with vertical flanks, into a lower, relatively thick photoresist layer (bottom resist). On account of the chemical amplification of the patterned top resist, this process has become known as CARL (chemical amplification of resist lines). During the etching of the substrate, the bottom resist serves as the actual mask. The bottom resist itself then has to be removed in a special etching process, for example using O2 or SO2. In particular during the etching of contact holes with a very high aspect ratio, photoresist masks of this type have the significant drawback that it is not possible to control the polymers formed from the resist during the etch. This can lead to a considerable reduction in the etching process window for very small structures.
Furthermore, there are known processes in which the auxiliary layer used is what is known as a hard mask. In German patent DE 195 04 434 C1, a photoresist layer on a mask layer made from a silicon-containing dielectric is exposed in accordance with a predetermined pattern and patterned using solvent. The photoresist layer is used to transfer the pattern to the mask layer, using a modified anisotropic plasma etching process in which the chemical component of the etch is dominant. Then, the photoresist is removed and the patterned mask layer can be used as a mask for a dry etching process for patterning the substrate. Furthermore, similar processes are known, in which hard masks made from polysilicon are used. The polysilicon hard mask layer is in this case deposited in a furnace process at temperatures of between 600° C. and 700° C., which can give rise to problems as a result of the thermal load imposed on the circuit structures which have already been produced. One general problem of the hard mask materials which have just been referred to is that they have to be opened up in a dedicated etching step. A further drawback is that they are not generally suitable—as in the example of polysilicon—for use as antireflection coatings.
Hitherto, antireflection organic layers have been disclosed, which are applied to the surface of the wafer by spin-on processes prior to the actual coating with the photoresist to be exposed using a track. However, these layers cannot be used as hard mask layers, and the reflection can only be reduced to approx. 10%. Furthermore, inorganic oxynitrides which are applied using a CVD process are known for use as antireflection layers, but the reflection cannot be reduced to below 10%. At least for use in oxide etching processes, these layers are likewise not suitable for use as hard mask layers.
Furthermore, it is known from documents U.S. Pat. Nos. 5,378,316, 5,656,128 and EP 0 808 481 B1 to use a hard-mask layer formed from carbon to produce patterns by photolithography. In these documents, it is proposed that the carbon hard mask layer be deposited by a PECVD (plasma enhanced chemical vapor deposition) process, so that hydrogen can be deliberately incorporated into the carbon layer. In this process, it is customary to set pressures of approx. 1-10 Torr of the plasma in the reactor chamber and substrate temperatures of around 400° C. The PECVD deposition gives rise to a highly compacted antireflection coating which already has very good properties as a hard mask and the reflective indices of which can be set by means of the process. This allows a balance to be achieved between optical performance and etching resistance. Production of the carbon hard mask layer by means of the PECVD process gives good results, provided that the deposition can be performed on planar patterns. However, if the deposition has to take place on a topographic pattern which has holes, trenches or elevations, the PECVD process has the drawback that the carbon layer cannot be optimally introduced into the trenches and holes and also does not have a planarizing action. A further drawback is that in general the hard mask quality of the carbon hard mask layer increases with increasing hardness, i.e. an increasing diamond fraction, in the layer and with a decrease in hydrogen content, but the two criteria can only be realized to a limited extent using the PECVD process. For example, the diamond content of the layers deposited by PECVD is virtually zero and the hydrogen content cannot be reduced to below 15%.
Moreover, it is known from the above-cited U.S. Pat. No. 5,378,316 to pattern the carbon hard mask layer not directly by means of the photoresist, but rather by means of an interlayer made from SiO2. This has the advantage that the photoresist layer can be made thinner, so that it is possible to obtain a greater degree of freedom when setting the process conditions of the lithography used in the patterning of the photoresist.
U.S. Pat. No. 5,981,398 describes a patterning process with a chlorine-containing plasma using a hard mask. The hard mask material described is, inter alia, an amorphous carbon layer which is produced by a HDP (high density plasma) CVD process. The etching processes described in this document serve to produce and pattern electrically conductive materials, in particular (Al) interconnect materials. However, there is no more accurate description of how the process is to be managed to ensure that a carbon hard mask layer of high quality can be achieved.